In a field effect transistor (“FET”), a capacitance is associated with a gate dielectric layer, which insulates a gate electrode from a channel disposed within a semiconductor substrate. As semiconductor devices continue to be scaled down to reduce power consumption, the demand for higher input FET capacitances has increased. The input capacitance of a FET may be increased by either reducing the thickness of the gate dielectric layer or increasing its dielectric constant.
Gate dielectric layers have historically been realized by bulk silicon dioxide, SiO2. To date, industry has been reducing the thickness of bulk silicon dioxide-based gate dielectric layers to increase input FET capacitances. However, at thicknesses of less than about 15 Å, bulk silicon dioxide becomes exceedingly susceptible to leakage currents tunneling through the gate dielectric layer. Thus, the leakage current problem is now becoming a practical concern.
To overcome this leakage current problem, industry has begun to explore various alternatives materials. These alternative materials have a dielectric constant greater than that of bulk silicon dioxide. As input FET capacitance is directly proportional to the dielectric constant of the gate dielectric layer and inversely proportional to the gate dielectric layer's thickness, it is believed that one of these alternative materials may enable the formation of a gate dielectric layer of a sufficient thickness to ameliorate the leakage current problem, while also increasing the input FET capacitance. Typical materials being investigated include metal-silicon-oxynitride and metal silicate, for example.
The use of such alternative materials as gate dielectric layers gives rise to other problems, however. The interface between the alternative materials under consideration and the underlying silicon substrate is of a poorer quality than the interface between bulk silicon dioxide and the silicon substrate. This poorer interface quality, attributable to several factors including an increased number of defects (e.g., dangling bonds) at the silicon interface, as well as the numbers of charges to become trapped by these defects. The trapped charges degrade device performance, reduce the reliability of the gate dielectric layer, and, therefore, reduce the FETs' so-called “mean time between failure.”